Performing testing utilizing staggered clocks

ABSTRACT

During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

FIELD OF THE INVENTION

The present invention relates to integrated circuit testing, and moreparticularly to performing in-system and ATE manufacturing testingduring a runtime of the system.

BACKGROUND

Within a multi-processor (e.g., multi-core) processing environment, oneof the processors (e.g., processing cores) may be tested (e.g., forstructural defects in hardware, etc.). However, the processor beingtested may share a voltage rail with additional processors within themulti-processor environment. This voltage rail may supply power to theprocessors. The testing of the single processor may produce a togglerate that may cause a voltage drop as a result of current fluctuationsproduced by the single processor being tested. This voltage drop maynegatively affect the other processors sharing the voltage rail with theprocessor being tested (e.g., by causing timing failures within thoseprocessors, etc.). Further, within an automatic test equipment (ATE)application environment, multiple processors sharing a single voltagerail may be tested simultaneously.

Single partitions within a processing core have grown large enough suchthat a toggle rate within a single partition of a single processing coremay cause a voltage drop with negative effects. There is therefore aneed to adjust a toggle rate within a single partition of a singleprocessing core being tested.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a flowchart of a method for performing testingutilizing staggered clocks, in accordance with an embodiment.

FIG. 2 illustrates a parallel processing unit, in accordance with anembodiment.

FIG. 3A illustrates a general processing cluster within the parallelprocessing unit of FIG. 2 , in accordance with an embodiment.

FIG. 3B illustrates a memory partition unit of the parallel processingunit of FIG. 2 , in accordance with an embodiment.

FIG. 4A illustrates the streaming multi-processor of FIG. 3A, inaccordance with an embodiment.

FIG. 4B is a conceptual diagram of a processing system implemented usingthe PPU of FIG. 2 , in accordance with an embodiment.

FIG. 4C illustrates an exemplary system in which the variousarchitecture and/or functionality of the various previous embodimentsmay be implemented.

FIG. 5 illustrates an exemplary computing environment during a runtimetest, in accordance with an embodiment.

FIG. 6 illustrates an exemplary scan architecture for a singlepartition, in accordance with an embodiment.

FIG. 7 illustrates an exemplary CPU cluster, in accordance with anembodiment.

FIG. 8 illustrates an exemplary staggering of clocks across quadrants ofa partition of a processing core, in accordance with an embodiment.

FIG. 9 illustrates an exemplary quadrant grouping within a partition, inaccordance with an embodiment.

DETAILED DESCRIPTION

It is desirable to monitor devices such as integrated circuits whilethey are operating to ensure that they are operating free of defects.Integrated circuits each include a set of electronic circuits (such asmultiple independent processing elements) on a single piece ofsemiconductor material (e.g., silicon, etc.).

To perform testing, during functional/normal operation of an integratedcircuit including multiple independent processing elements (such asprocessors), a selected independent processing element is taken offline(e.g., by stopping functional operation of the independent processingelement), and the functionality of the selected independent processingelement is then tested while the remaining independent processingelements continue functional operation (e.g., standardapplication-specific operations). To minimize voltage drops resultingfrom current fluctuations produced by the testing of the processingelement, clocks used to synchronize operations within each partition ofa processing element are staggered. This varies the toggle rate withinthe partition of the processing element during the testing of eachprocessing core, thereby reducing the resulting voltage drop.

FIG. 1 illustrates a flowchart of a method 100 for performing testingutilizing staggered clocks, in accordance with an embodiment. Althoughmethod 100 is described in the context of a processing unit, the method100 may also be performed by a program, custom circuitry, or by acombination of custom circuitry and a program. For example, the method100 may be executed by a GPU (graphics processing unit), CPU (centralprocessing unit), or any processing element. Furthermore, persons ofordinary skill in the art will understand that any system that performsmethod 100 is within the scope and spirit of embodiments of the presentinvention.

As shown in operation 102, clocks are staggered within a computingelement. In one embodiment, the computing element may include a singlepartition of a single processing core. For example, the singleprocessing core may have a plurality of different partitions. In anotherembodiment, the single processing core may include a processor such as acentral processing unit (CPU), a graphics processing unit (GPU), a deeplearning accelerator, etc. In yet another embodiment, each clock withinthe computing element may include a clock generator that generatespulses used to synchronize operations within the computing element.

Additionally, in one embodiment, the single processing core may be oneof a plurality of processing cores within a system. For example, thesystem may include a multi-core processing environment. In anotherexample, the system may include an integrated circuit having multiplecomputing clusters, where each computing cluster includes multipleindependent processing cores. In yet another example, the integratedcircuit may include a system on a chip (SoC) that includes components ofa computer or other electronic system. In still another example, theintegrated circuit may include an application-specific integratedcircuit (ASIC).

Further, in one embodiment, application-specific operations may beperformed by the processing cores within the system. For example, theapplication-specific operations may include specificapplication-specific tasks performed by the independent processingcores. In another example, the standard operations may includeapplication-specific tasks for which the system is designed. In yetanother example, the application-specific tasks may include autonomousnavigation/driving operations, robotics manipulation operations,industrial automation operations, etc.

Further still, in one embodiment, the processing core may include asingle independent processing core selected from a cluster ofindependent processing cores that are currently performingapplication-specific operations. In another embodiment, the processingcore may be selected to be taken offline for testing. For example, theprocessing core may be taken offline in response to a testing taskissued to the processing core by a system software scheduler. In anotherembodiment, the testing task may be different from theapplication-specific tasks performed by the remaining processing coreswithin the cluster that enable the functional operation of the system.

Also, in one embodiment, in response to receiving the testing task fromthe system software scheduler, the processing core may be broughtoffline. In another embodiment, the processing core may be broughtoffline by removing an identifier of the processing core from a view ofan operating system (OS) being run within the system. In yet anotherembodiment, after being brought offline, the clocks may be staggeredwithin each partition within the processing core.

In addition, in one embodiment, the entire system may be offline whenthe clocks are staggered within the processing core. In anotherembodiment, staggering the clocks within the computing element mayinclude creating a plurality of different clipped clocks within thecomputing element. In yet another embodiment, a clipped clock may becreated for each of a plurality of different portions of the computingelement, where each of the clipped clocks are different (e.g., have adifferent waveform, etc.).

For example, a first clipped clock may be created for a first portion ofthe computing element, and a second clipped clock may be created for asecond portion of the computing element, where the first clipped clockhas a different waveform than the second clipped clock.

Furthermore, in one embodiment, each of a plurality of differentportions of the computing element may include a segment of a singlepartition of a processing core. In another embodiment, each of theclipped clocks may be assigned to a different predetermined portion ofthe computing element. In yet another embodiment, staggering the clocksmay be performed utilizing an existing clock source within the system.For example, the creation of a new clock source may be avoided whenstaggering the clocks.

Further still, in one embodiment, a clipped clock may be created for aportion of the computing element by manipulating one or more clockgaters within the portion to generate alternate waveforms. For example,each scan clock within the portion of the computing element may have anassociated clock gater that drives the scan clock. In another example, aport (e.g., a test enable port) of the clock gater may be connected to acontroller. In yet another example, the controller may generate one ormore signals that are sent to the clock gater. In still anotherembodiment, these signals may shift the resulting waveform of the scanclock associated with the clock gater.

Also, in one embodiment, the manipulated clock gaters within the portionmay be driven by a fast clock within the system to create the clippedclock within the portion. For example, the system may include a fastclock and a slow clock, where the fast clock has a greater frequencythan the slow clock. In another example, the portion of the computingelement may be driven by the slow clock during normal operation. In yetanother example, during testing, the computing element may be driven bythe fast clock. In still another example, as the fast clock is fed intothe manipulated clock gaters, a clipped clock is produced by theassociated scan clock.

Additionally, as shown in operation 104, testing of the computingelement is performed, utilizing the staggered clocks. In one embodiment,each of the plurality of different portions of the computing element maybe tested utilizing the clipped clock corresponding to the portion. Forexample, a first clipped clock may be used to test a first portion ofthe computing element, and a second clipped clock may be used to test asecond portion of the computing element, where the first clipped clockhas a different waveform than the second clipped clock.

In this way, a toggle rate may be varied throughout a single partitionof a single processing core during the testing of the processing core,utilizing the staggered clocks. This may reduce a voltage drop caused bythe single partition during testing, which may eliminate timing failuresfor additional processing cores located on the same voltage rail as theprocessing core being tested. This solution may also be implemented intoexisting processing core infrastructures without modification, and maymake hardware testing more reliable/robust. This may also improve testquality within an automated test equipment (ATE) environment.

In yet another embodiment, the testing may be performed utilizing aparallel processing unit (PPU) such as the PPU 200 illustrated in FIG. 2.

More illustrative information will now be set forth regarding variousoptional architectures and features with which the foregoing frameworkmay be implemented, per the desires of the user. It should be stronglynoted that the following information is set forth for illustrativepurposes and should not be construed as limiting in any manner. Any ofthe following features may be optionally incorporated with or withoutthe exclusion of other features described.

Parallel Processing Architecture

FIG. 2 illustrates a parallel processing unit (PPU) 200, in accordancewith an embodiment. In an embodiment, the PPU 200 is a multi-threadedprocessor that is implemented on one or more integrated circuit devices.The PPU 200 is a latency hiding architecture designed to process manythreads in parallel. A thread (i.e., a thread of execution) is aninstantiation of a set of instructions configured to be executed by thePPU 200. In an embodiment, the PPU 200 is a graphics processing unit(GPU) configured to implement a graphics rendering pipeline forprocessing three-dimensional (3D) graphics data in order to generatetwo-dimensional (2D) image data for display on a display device such asa liquid crystal display (LCD) device. In other embodiments, the PPU 200may be utilized for performing general-purpose computations. While oneexemplary parallel processor is provided herein for illustrativepurposes, it should be strongly noted that such processor is set forthfor illustrative purposes only, and that any processor may be employedto supplement and/or substitute for the same.

One or more PPUs 200 may be configured to accelerate thousands of HighPerformance Computing (HPC), data center, and machine learningapplications. The PPU 200 may be configured to accelerate numerous deeplearning systems and applications including autonomous vehicleplatforms, deep learning, high-accuracy speech, image, and textrecognition systems, intelligent video analytics, molecular simulations,drug discovery, disease diagnosis, weather forecasting, big dataanalytics, astronomy, molecular dynamics simulation, financial modeling,robotics, factory automation, real-time language translation, onlinesearch optimizations, and personalized user recommendations, and thelike.

As shown in FIG. 2 , the PPU 200 includes an Input/Output (I/O) unit205, a front end unit 215, a scheduler unit 220, a work distributionunit 225, a hub 230, a crossbar (Xbar) 270, one or more generalprocessing clusters (GPCs) 250, and one or more partition units 280. ThePPU 200 may be connected to a host processor or other PPUs 200 via oneor more high-speed NVLink 210 interconnect. The PPU 200 may be connectedto a host processor or other peripheral devices via an interconnect 202.The PPU 200 may also be connected to a local memory comprising a numberof memory devices 204. In an embodiment, the local memory may comprise anumber of dynamic random access memory (DRAM) devices. The DRAM devicesmay be configured as a high-bandwidth memory (HBM) subsystem, withmultiple DRAM dies stacked within each device.

The NVLink 210 interconnect enables systems to scale and include one ormore PPUs 200 combined with one or more CPUs, supports cache coherencebetween the PPUs 200 and CPUs, and CPU mastering. Data and/or commandsmay be transmitted by the NVLink 210 through the hub 230 to/from otherunits of the PPU 200 such as one or more copy engines, a video encoder,a video decoder, a power management unit, etc. (not explicitly shown).The NVLink 210 is described in more detail in conjunction with FIG. 4B.

The I/O unit 205 is configured to transmit and receive communications(i.e., commands, data, etc.) from a host processor (not shown) over theinterconnect 202. The I/O unit 205 may communicate with the hostprocessor directly via the interconnect 202 or through one or moreintermediate devices such as a memory bridge. In an embodiment, the I/Ounit 205 may communicate with one or more other processors, such as oneor more the PPUs 200 via the interconnect 202. In an embodiment, the I/Ounit 205 implements a Peripheral Component Interconnect Express (PCIe)interface for communications over a PCIe bus and the interconnect 202 isa PCIe bus. In alternative embodiments, the I/O unit 205 may implementother types of well-known interfaces for communicating with externaldevices.

The I/O unit 205 decodes packets received via the interconnect 202. Inan embodiment, the packets represent commands configured to cause thePPU 200 to perform various operations. The I/O unit 205 transmits thedecoded commands to various other units of the PPU 200 as the commandsmay specify. For example, some commands may be transmitted to the frontend unit 215. Other commands may be transmitted to the hub 230 or otherunits of the PPU 200 such as one or more copy engines, a video encoder,a video decoder, a power management unit, etc. (not explicitly shown).In other words, the I/O unit 205 is configured to route communicationsbetween and among the various logical units of the PPU 200.

In an embodiment, a program executed by the host processor encodes acommand stream in a buffer that provides workloads to the PPU 200 forprocessing. A workload may comprise several instructions and data to beprocessed by those instructions. The buffer is a region in a memory thatis accessible (i.e., read/write) by both the host processor and the PPU200. For example, the I/O unit 205 may be configured to access thebuffer in a system memory connected to the interconnect 202 via memoryrequests transmitted over the interconnect 202. In an embodiment, thehost processor writes the command stream to the buffer and thentransmits a pointer to the start of the command stream to the PPU 200.The front end unit 215 receives pointers to one or more command streams.The front end unit 215 manages the one or more streams, reading commandsfrom the streams and forwarding commands to the various units of the PPU200.

The front end unit 215 is coupled to a scheduler unit 220 thatconfigures the various GPCs 250 to process tasks defined by the one ormore streams. The scheduler unit 220 is configured to track stateinformation related to the various tasks managed by the scheduler unit220. The state may indicate which GPC 250 a task is assigned to, whetherthe task is active or inactive, a priority level associated with thetask, and so forth. The scheduler unit 220 manages the execution of aplurality of tasks on the one or more GPCs 250.

The scheduler unit 220 is coupled to a work distribution unit 225 thatis configured to dispatch tasks for execution on the GPCs 250. The workdistribution unit 225 may track a number of scheduled tasks receivedfrom the scheduler unit 220. In an embodiment, the work distributionunit 225 manages a pending task pool and an active task pool for each ofthe GPCs 250. The pending task pool may comprise a number of slots(e.g., 32 slots) that contain tasks assigned to be processed by aparticular GPC 250. The active task pool may comprise a number of slots(e.g., 4 slots) for tasks that are actively being processed by the GPCs250. As a GPC 250 finishes the execution of a task, that task is evictedfrom the active task pool for the GPC 250 and one of the other tasksfrom the pending task pool is selected and scheduled for execution onthe GPC 250. If an active task has been idle on the GPC 250, such aswhile waiting for a data dependency to be resolved, then the active taskmay be evicted from the GPC 250 and returned to the pending task poolwhile another task in the pending task pool is selected and scheduledfor execution on the GPC 250.

The work distribution unit 225 communicates with the one or more GPCs250 via XBar 270. The XBar 270 is an interconnect network that couplesmany of the units of the PPU 200 to other units of the PPU 200. Forexample, the XBar 270 may be configured to couple the work distributionunit 225 to a particular GPC 250. Although not shown explicitly, one ormore other units of the PPU 200 may also be connected to the XBar 270via the hub 230.

The tasks are managed by the scheduler unit 220 and dispatched to a GPC250 by the work distribution unit 225. The GPC 250 is configured toprocess the task and generate results. The results may be consumed byother tasks within the GPC 250, routed to a different GPC 250 via theXBar 270, or stored in the memory 204. The results can be written to thememory 204 via the partition units 280, which implement a memoryinterface for reading and writing data to/from the memory 204. Theresults can be transmitted to another PPU 200 or CPU via the NVLink 210.In an embodiment, the PPU 200 includes a number U of partition units 280that is equal to the number of separate and distinct memory devices 204coupled to the PPU 200. A partition unit 280 will be described in moredetail below in conjunction with FIG. 3B.

In an embodiment, a host processor executes a driver kernel thatimplements an application programming interface (API) that enables oneor more applications executing on the host processor to scheduleoperations for execution on the PPU 200. In an embodiment, multiplecompute applications are simultaneously executed by the PPU 200 and thePPU 200 provides isolation, quality of service (QoS), and independentaddress spaces for the multiple compute applications. An application maygenerate instructions (i.e., API calls) that cause the driver kernel togenerate one or more tasks for execution by the PPU 200. The driverkernel outputs tasks to one or more streams being processed by the PPU200. Each task may comprise one or more groups of related threads,referred to herein as a warp. In an embodiment, a warp comprises 32related threads that may be executed in parallel. Cooperating threadsmay refer to a plurality of threads including instructions to performthe task and that may exchange data through shared memory. Threads andcooperating threads are described in more detail in conjunction withFIG. 4A.

FIG. 3A illustrates a GPC 250 of the PPU 200 of FIG. 2 , in accordancewith an embodiment. As shown in FIG. 3A, each GPC 250 includes a numberof hardware units for processing tasks. In an embodiment, each GPC 250includes a pipeline manager 310, a pre-raster operations unit (PROP)315, a raster engine 325, a work distribution crossbar (WDX) 380, amemory management unit (MMU) 390, and one or more Data ProcessingClusters (DPCs) 320. It will be appreciated that the GPC 250 of FIG. 3Amay include other hardware units in lieu of or in addition to the unitsshown in FIG. 3A.

In an embodiment, the operation of the GPC 250 is controlled by thepipeline manager 310. The pipeline manager 310 manages the configurationof the one or more DPCs 320 for processing tasks allocated to the GPC250. In an embodiment, the pipeline manager 310 may configure at leastone of the one or more DPCs 320 to implement at least a portion of agraphics rendering pipeline. For example, a DPC 320 may be configured toexecute a vertex shader program on the programmable streamingmultiprocessor (SM) 340. The pipeline manager 310 may also be configuredto route packets received from the work distribution unit 225 to theappropriate logical units within the GPC 250. For example, some packetsmay be routed to fixed function hardware units in the PROP 315 and/orraster engine 325 while other packets may be routed to the DPCs 320 forprocessing by the primitive engine 335 or the SM 340. In an embodiment,the pipeline manager 310 may configure at least one of the one or moreDPCs 320 to implement a neural network model and/or a computingpipeline.

The PROP unit 315 is configured to route data generated by the rasterengine 325 and the DPCs 320 to a Raster Operations (ROP) unit, describedin more detail in conjunction with FIG. 3B. The PROP unit 315 may alsobe configured to perform optimizations for color blending, organizepixel data, perform address translations, and the like.

The raster engine 325 includes a number of fixed function hardware unitsconfigured to perform various raster operations. In an embodiment, theraster engine 325 includes a setup engine, a coarse raster engine, aculling engine, a clipping engine, a fine raster engine, and a tilecoalescing engine. The setup engine receives transformed vertices andgenerates plane equations associated with the geometric primitivedefined by the vertices. The plane equations are transmitted to thecoarse raster engine to generate coverage information (e.g., an x,ycoverage mask for a tile) for the primitive. The output of the coarseraster engine is transmitted to the culling engine where fragmentsassociated with the primitive that fail a z-test are culled, andtransmitted to a clipping engine where fragments lying outside a viewingfrustum are clipped. Those fragments that survive clipping and cullingmay be passed to the fine raster engine to generate attributes for thepixel fragments based on the plane equations generated by the setupengine. The output of the raster engine 325 comprises fragments to beprocessed, for example, by a fragment shader implemented within a DPC320.

Each DPC 320 included in the GPC 250 includes an M-Pipe Controller (MPC)330, a primitive engine 335, and one or more SMs 340. The MPC 330controls the operation of the DPC 320, routing packets received from thepipeline manager 310 to the appropriate units in the DPC 320. Forexample, packets associated with a vertex may be routed to the primitiveengine 335, which is configured to fetch vertex attributes associatedwith the vertex from the memory 204. In contrast, packets associatedwith a shader program may be transmitted to the SM 340.

The SM 340 comprises a programmable streaming processor that isconfigured to process tasks represented by a number of threads. Each SM340 is multi-threaded and configured to execute a plurality of threads(e.g., 32 threads) from a particular group of threads concurrently. Inan embodiment, the SM 340 implements a SIMD (Single-Instruction,Multiple-Data) architecture where each thread in a group of threads(i.e., a warp) is configured to process a different set of data based onthe same set of instructions. All threads in the group of threadsexecute the same instructions. In another embodiment, the SM 340implements a SIMT (Single-Instruction, Multiple Thread) architecturewhere each thread in a group of threads is configured to process adifferent set of data based on the same set of instructions, but whereindividual threads in the group of threads are allowed to diverge duringexecution. In an embodiment, a program counter, call stack, andexecution state is maintained for each warp, enabling concurrencybetween warps and serial execution within warps when threads within thewarp diverge. In another embodiment, a program counter, call stack, andexecution state is maintained for each individual thread, enabling equalconcurrency between all threads, within and between warps. Whenexecution state is maintained for each individual thread, threadsexecuting the same instructions may be converged and executed inparallel for maximum efficiency. The SM 340 will be described in moredetail below in conjunction with FIG. 4A.

The MMU 390 provides an interface between the GPC 250 and the partitionunit 280. The MMU 390 may provide translation of virtual addresses intophysical addresses, memory protection, and arbitration of memoryrequests. In an embodiment, the MMU 390 provides one or more translationlookaside buffers (TLBs) for performing translation of virtual addressesinto physical addresses in the memory 204.

FIG. 3B illustrates a memory partition unit 280 of the PPU 200 of FIG. 2, in accordance with an embodiment. As shown in FIG. 3B, the memorypartition unit 280 includes a Raster Operations (ROP) unit 350, a leveltwo (L2) cache 360, and a memory interface 370. The memory interface 370is coupled to the memory 204. Memory interface 370 may implement 32, 64,128, 1024-bit data buses, or the like, for high-speed data transfer. Inan embodiment, the PPU 200 incorporates U memory interfaces 370, onememory interface 370 per pair of partition units 280, where each pair ofpartition units 280 is connected to a corresponding memory device 204.For example, PPU 200 may be connected to up to Y memory devices 204,such as high bandwidth memory stacks or graphics double-data-rate,version 5, synchronous dynamic random access memory, or other types ofpersistent storage.

In an embodiment, the memory interface 370 implements an HBM2 memoryinterface and Y equals half U. In an embodiment, the HBM2 memory stacksare located on the same physical package as the PPU 200, providingsubstantial power and area savings compared with conventional GDDR5SDRAM systems. In an embodiment, each HBM2 stack includes four memorydies and Y equals 4, with HBM2 stack including two 128-bit channels perdie for a total of 8 channels and a data bus width of 1024 bits.

In an embodiment, the memory 204 supports Single-Error CorrectingDouble-Error Detecting (SECDED) Error Correction Code (ECC) to protectdata. ECC provides higher reliability for compute applications that aresensitive to data corruption. Reliability is especially important inlarge-scale cluster computing environments where PPUs 200 process verylarge datasets and/or run applications for extended periods.

In an embodiment, the PPU 200 implements a multi-level memory hierarchy.In an embodiment, the memory partition unit 280 supports a unifiedmemory to provide a single unified virtual address space for CPU and PPU200 memory, enabling data sharing between virtual memory systems. In anembodiment the frequency of accesses by a PPU 200 to memory located onother processors is traced to ensure that memory pages are moved to thephysical memory of the PPU 200 that is accessing the pages morefrequently. In an embodiment, the NVLink 210 supports addresstranslation services allowing the PPU 200 to directly access a CPU'spage tables and providing full access to CPU memory by the PPU 200.

In an embodiment, copy engines transfer data between multiple PPUs 200or between PPUs 200 and CPUs. The copy engines can generate page faultsfor addresses that are not mapped into the page tables. The memorypartition unit 280 can then service the page faults, mapping theaddresses into the page table, after which the copy engine can performthe transfer. In a conventional system, memory is pinned (i.e.,non-pageable) for multiple copy engine operations between multipleprocessors, substantially reducing the available memory. With hardwarepage faulting, addresses can be passed to the copy engines withoutworrying if the memory pages are resident, and the copy process istransparent.

Data from the memory 204 or other system memory may be fetched by thememory partition unit 280 and stored in the L2 cache 360, which islocated on-chip and is shared between the various GPCs 250. As shown,each memory partition unit 280 includes a portion of the L2 cache 360associated with a corresponding memory device 204. Lower level cachesmay then be implemented in various units within the GPCs 250. Forexample, each of the SMs 340 may implement a level one (L1) cache. TheL1 cache is private memory that is dedicated to a particular SM 340.Data from the L2 cache 360 may be fetched and stored in each of the L1caches for processing in the functional units of the SMs 340. The L2cache 360 is coupled to the memory interface 370 and the XBar 270.

The ROP unit 350 performs graphics raster operations related to pixelcolor, such as color compression, pixel blending, and the like. The ROPunit 350 also implements depth testing in conjunction with the rasterengine 325, receiving a depth for a sample location associated with apixel fragment from the culling engine of the raster engine 325. Thedepth is tested against a corresponding depth in a depth buffer for asample location associated with the fragment. If the fragment passes thedepth test for the sample location, then the ROP unit 350 updates thedepth buffer and transmits a result of the depth test to the rasterengine 325. It will be appreciated that the number of partition units280 may be different than the number of GPCs 250 and, therefore, eachROP unit 350 may be coupled to each of the GPCs 250. The ROP unit 350tracks packets received from the different GPCs 250 and determines whichGPC 250 that a result generated by the ROP unit 350 is routed to throughthe Xbar 270. Although the ROP unit 350 is included within the memorypartition unit 280 in FIG. 3B, in other embodiment, the ROP unit 350 maybe outside of the memory partition unit 280. For example, the ROP unit350 may reside in the GPC 250 or another unit.

FIG. 4A illustrates the streaming multi-processor 340 of FIG. 3A, inaccordance with an embodiment. As shown in FIG. 4A, the SM 340 includesan instruction cache 405, one or more scheduler units 410(K), a registerfile 420, one or more processing cores 450, one or more special functionunits (SFUs) 452, one or more load/store units (LSUs) 454, aninterconnect network 480, a shared memory/L1 cache 470.

As described above, the work distribution unit 225 dispatches tasks forexecution on the GPCs 250 of the PPU 200. The tasks are allocated to aparticular DPC 320 within a GPC 250 and, if the task is associated witha shader program, the task may be allocated to an SM 340. The schedulerunit 410(K) receives the tasks from the work distribution unit 225 andmanages instruction scheduling for one or more thread blocks assigned tothe SM 340. The scheduler unit 410(K) schedules thread blocks forexecution as warps of parallel threads, where each thread block isallocated at least one warp. In an embodiment, each warp executes 32threads. The scheduler unit 410(K) may manage a plurality of differentthread blocks, allocating the warps to the different thread blocks andthen dispatching instructions from the plurality of differentcooperative groups to the various functional units (i.e., cores 450,SFUs 452, and LSUs 454) during each clock cycle.

Cooperative Groups is a programming model for organizing groups ofcommunicating threads that allows developers to express the granularityat which threads are communicating, enabling the expression of richer,more efficient parallel decompositions. Cooperative launch APIs supportsynchronization amongst thread blocks for the execution of parallelalgorithms. Conventional programming models provide a single, simpleconstruct for synchronizing cooperating threads: a barrier across allthreads of a thread block (i.e., the syncthreads( ) function). However,programmers would often like to define groups of threads at smaller thanthread block granularities and synchronize within the defined groups toenable greater performance, design flexibility, and software reuse inthe form of collective group-wide function interfaces.

Cooperative Groups enables programmers to define groups of threadsexplicitly at sub-block (i.e., as small as a single thread) andmulti-block granularities, and to perform collective operations such assynchronization on the threads in a cooperative group. The programmingmodel supports clean composition across software boundaries, so thatlibraries and utility functions can synchronize safely within theirlocal context without having to make assumptions about convergence.Cooperative Groups primitives enable new patterns of cooperativeparallelism, including producer-consumer parallelism, opportunisticparallelism, and global synchronization across an entire grid of threadblocks.

A dispatch unit 415 is configured to transmit instructions to one ormore of the functional units. In the embodiment, the scheduler unit410(K) includes two dispatch units 415 that enable two differentinstructions from the same warp to be dispatched during each clockcycle. In alternative embodiments, each scheduler unit 410(K) mayinclude a single dispatch unit 415 or additional dispatch units 415.

Each SM 340 includes a register file 420 that provides a set ofregisters for the functional units of the SM 340. In an embodiment, theregister file 420 is divided between each of the functional units suchthat each functional unit is allocated a dedicated portion of theregister file 420. In another embodiment, the register file 420 isdivided between the different warps being executed by the SM 340. Theregister file 420 provides temporary storage for operands connected tothe data paths of the functional units.

Each SM 340 comprises L processing cores 450. In an embodiment, the SM340 includes a large number (e.g., 128, etc.) of distinct processingcores 450. Each core 450 may include a fully-pipelined,single-precision, double-precision, and/or mixed precision processingunit that includes a floating point arithmetic logic unit and an integerarithmetic logic unit. In an embodiment, the floating point arithmeticlogic units implement the IEEE 754-2008 standard for floating pointarithmetic. In an embodiment, the cores 450 include 64 single-precision(32-bit) floating point cores, 64 integer cores, 32 double-precision(64-bit) floating point cores, and 8 tensor cores.

Tensor cores configured to perform matrix operations, and, in anembodiment, one or more tensor cores are included in the cores 450. Inparticular, the tensor cores are configured to perform deep learningmatrix arithmetic, such as convolution operations for neural networktraining and inferencing. In an embodiment, each tensor core operates ona 4×4 matrix and performs a matrix multiply and accumulate operationD=A×B+C, where A, B, C, and D are 4×4 matrices.

In an embodiment, the matrix multiply inputs A and B are 16-bit floatingpoint matrices, while the accumulation matrices C and D may be 16-bitfloating point or 32-bit floating point matrices. Tensor Cores operateon 16-bit floating point input data with 32-bit floating pointaccumulation. The 16-bit floating point multiply requires 64 operationsand results in a full precision product that is then accumulated using32-bit floating point addition with the other intermediate products fora 4×4×4 matrix multiply. In practice, Tensor Cores are used to performmuch larger two-dimensional or higher dimensional matrix operations,built up from these smaller elements. An API, such as CUDA 9 C++ API,exposes specialized matrix load, matrix multiply and accumulate, andmatrix store operations to efficiently use Tensor Cores from a CUDA-C++program. At the CUDA level, the warp-level interface assumes 16×16 sizematrices spanning all 32 threads of the warp.

Each SM 340 also comprises M SFUs 452 that perform special functions(e.g., attribute evaluation, reciprocal square root, and the like). Inan embodiment, the SFUs 452 may include a tree traversal unit configuredto traverse a hierarchical tree data structure. In an embodiment, theSFUs 452 may include texture unit configured to perform texture mapfiltering operations. In an embodiment, the texture units are configuredto load texture maps (e.g., a 2D array of texels) from the memory 204and sample the texture maps to produce sampled texture values for use inshader programs executed by the SM 340. In an embodiment, the texturemaps are stored in the shared memory/L1 cache 370. The texture unitsimplement texture operations such as filtering operations using mip-maps(i.e., texture maps of varying levels of detail). In an embodiment, eachSM 240 includes two texture units.

Each SM 340 also comprises N LSUs 454 that implement load and storeoperations between the shared memory/L1 cache 470 and the register file420. Each SM 340 includes an interconnect network 480 that connects eachof the functional units to the register file 420 and the LSU 454 to theregister file 420, shared memory/L1 cache 470. In an embodiment, theinterconnect network 480 is a crossbar that can be configured to connectany of the functional units to any of the registers in the register file420 and connect the LSUs 454 to the register file and memory locationsin shared memory/L1 cache 470.

The shared memory/L1 cache 470 is an array of on-chip memory that allowsfor data storage and communication between the SM 340 and the primitiveengine 335 and between threads in the SM 340. In an embodiment, theshared memory/L1 cache 470 comprises 128 KB of storage capacity and isin the path from the SM 340 to the partition unit 280. The sharedmemory/L1 cache 470 can be used to cache reads and writes. One or moreof the shared memory/L1 cache 470, L2 cache 360, and memory 204 arebacking stores.

Combining data cache and shared memory functionality into a singlememory block provides the best overall performance for both types ofmemory accesses. The capacity is usable as a cache by programs that donot use shared memory. For example, if shared memory is configured touse half of the capacity, texture and load/store operations can use theremaining capacity. Integration within the shared memory/L1 cache 470enables the shared memory/L1 cache 470 to function as a high-throughputconduit for streaming data while simultaneously providing high-bandwidthand low-latency access to frequently reused data.

When configured for general purpose parallel computation, a simplerconfiguration can be used compared with graphics processing.Specifically, the fixed function graphics processing units shown in FIG.2 , are bypassed, creating a much simpler programming model. In thegeneral purpose parallel computation configuration, the workdistribution unit 225 assigns and distributes blocks of threads directlyto the DPCs 320. The threads in a block execute the same program, usinga unique thread ID in the calculation to ensure each thread generatesunique results, using the SM 340 to execute the program and performcalculations, shared memory/L1 cache 470 to communicate between threads,and the LSU 454 to read and write global memory through the sharedmemory/L1 cache 470 and the memory partition unit 280. When configuredfor general purpose parallel computation, the SM 340 can also writecommands that the scheduler unit 220 can use to launch new work on theDPCs 320.

The PPU 200 may be included in a desktop computer, a laptop computer, atablet computer, servers, supercomputers, a smart-phone (e.g., awireless, hand-held device), personal digital assistant (PDA), a digitalcamera, a vehicle, a head mounted display, a hand-held electronicdevice, and the like. In an embodiment, the PPU 200 is embodied on asingle semiconductor substrate. In another embodiment, the PPU 200 isincluded in a system-on-a-chip (SoC) along with one or more otherdevices such as additional PPUs 200, the memory 204, a reducedinstruction set computer (RISC) CPU, a memory management unit (MMU), adigital-to-analog converter (DAC), and the like.

In an embodiment, the PPU 200 may be included on a graphics card thatincludes one or more memory devices 204. The graphics card may beconfigured to interface with a PCIe slot on a motherboard of a desktopcomputer. In yet another embodiment, the PPU 200 may be an integratedgraphics processing unit (iGPU) or parallel processor included in thechipset of the motherboard.

Exemplary Computing System

Systems with multiple GPUs and CPUs are used in a variety of industriesas developers expose and leverage more parallelism in applications suchas artificial intelligence computing. High-performance GPU-acceleratedsystems with tens to many thousands of compute nodes are deployed indata centers, research facilities, and supercomputers to solve everlarger problems. As the number of processing devices within thehigh-performance systems increases, the communication and data transfermechanisms need to scale to support the increased bandwidth.

FIG. 4B is a conceptual diagram of a processing system 400 implementedusing the PPU 200 of FIG. 2 , in accordance with an embodiment. Theexemplary system 465 may be configured to implement the method 100 shownin FIG. 1 . The processing system 400 includes a CPU 430, switch 410,and multiple PPUs 200 each and respective memories 204. The NVLink 210provides high-speed communication links between each of the PPUs 200.Although a particular number of NVLink 210 and interconnect 202connections are illustrated in FIG. 4B, the number of connections toeach PPU 200 and the CPU 430 may vary. The switch 410 interfaces betweenthe interconnect 202 and the CPU 430. The PPUs 200, memories 204, andNVLinks 210 may be situated on a single semiconductor platform to form aparallel processing module 425. In an embodiment, the switch 410supports two or more protocols to interface between various differentconnections and/or links.

In another embodiment (not shown), the NVLink 210 provides one or morehigh-speed communication links between each of the PPUs 200 and the CPU430 and the switch 410 interfaces between the interconnect 202 and eachof the PPUs 200. The PPUs 200, memories 204, and interconnect 202 may besituated on a single semiconductor platform to form a parallelprocessing module 425. In yet another embodiment (not shown), theinterconnect 202 provides one or more communication links between eachof the PPUs 200 and the CPU 430 and the switch 410 interfaces betweeneach of the PPUs 200 using the NVLink 210 to provide one or morehigh-speed communication links between the PPUs 200. In anotherembodiment (not shown), the NVLink 210 provides one or more high-speedcommunication links between the PPUs 200 and the CPU 430 through theswitch 410. In yet another embodiment (not shown), the interconnect 202provides one or more communication links between each of the PPUs 200directly. One or more of the NVLink 210 high-speed communication linksmay be implemented as a physical NVLink interconnect or either anon-chip or on-die interconnect using the same protocol as the NVLink210.

In the context of the present description, a single semiconductorplatform may refer to a sole unitary semiconductor-based integratedcircuit fabricated on a die or chip. It should be noted that the termsingle semiconductor platform may also refer to multi-chip modules withincreased connectivity which simulate on-chip operation and makesubstantial improvements over utilizing a conventional busimplementation. Of course, the various circuits or devices may also besituated separately or in various combinations of semiconductorplatforms per the desires of the user. Alternately, the parallelprocessing module 425 may be implemented as a circuit board substrateand each of the PPUs 200 and/or memories 204 may be packaged devices. Inan embodiment, the CPU 430, switch 410, and the parallel processingmodule 425 are situated on a single semiconductor platform.

In an embodiment, the signaling rate of each NVLink 210 is 20 to 25Gigabits/second and each PPU 200 includes six NVLink 210 interfaces (asshown in FIG. 4B, five NVLink 210 interfaces are included for each PPU200). Each NVLink 210 provides a data transfer rate of 25Gigabytes/second in each direction, with six links providing 300Gigabytes/second. The NVLinks 210 can be used exclusively for PPU-to-PPUcommunication as shown in FIG. 4B, or some combination of PPU-to-PPU andPPU-to-CPU, when the CPU 430 also includes one or more NVLink 210interfaces.

In an embodiment, the NVLink 210 allows direct load/store/atomic accessfrom the CPU 430 to each PPU's 200 memory 204. In an embodiment, theNVLink 210 supports coherency operations, allowing data read from thememories 204 to be stored in the cache hierarchy of the CPU 430,reducing cache access latency for the CPU 430. In an embodiment, theNVLink 210 includes support for Address Translation Services (ATS),allowing the PPU 200 to directly access page tables within the CPU 430.One or more of the NVLinks 210 may also be configured to operate in alow-power mode.

FIG. 4C illustrates an exemplary system 465 in which the variousarchitecture and/or functionality of the various previous embodimentsmay be implemented. The exemplary system 465 may be configured toimplement the method 100 shown in FIG. 1 .

As shown, a system 465 is provided including at least one centralprocessing unit 430 that is connected to a communication bus 475. Thecommunication bus 475 may be implemented using any suitable protocol,such as PCI (Peripheral Component Interconnect), PCI-Express, AGP(Accelerated Graphics Port), HyperTransport, or any other bus orpoint-to-point communication protocol(s). The system 465 also includes amain memory 440. Control logic (software) and data are stored in themain memory 440 which may take the form of random access memory (RAM).

The system 465 also includes input devices 460, the parallel processingsystem 425, and display devices 445, i.e. a conventional CRT (cathoderay tube), LCD (liquid crystal display), LED (light emitting diode),plasma display or the like. User input may be received from the inputdevices 460, e.g., keyboard, mouse, touchpad, microphone, and the like.Each of the foregoing modules and/or devices may even be situated on asingle semiconductor platform to form the system 465. Alternately, thevarious modules may also be situated separately or in variouscombinations of semiconductor platforms per the desires of the user.

Further, the system 465 may be coupled to a network (e.g., atelecommunications network, local area network (LAN), wireless network,wide area network (WAN) such as the Internet, peer-to-peer network,cable network, or the like) through a network interface 435 forcommunication purposes.

The system 465 may also include a secondary storage (not shown). Thesecondary storage includes, for example, a hard disk drive and/or aremovable storage drive, representing a floppy disk drive, a magnetictape drive, a compact disk drive, digital versatile disk (DVD) drive,recording device, universal serial bus (USB) flash memory. The removablestorage drive reads from and/or writes to a removable storage unit in awell-known manner.

Computer programs, or computer control logic algorithms, may be storedin the main memory 440 and/or the secondary storage. Such computerprograms, when executed, enable the system 465 to perform variousfunctions. The memory 440, the storage, and/or any other storage arepossible examples of computer-readable media.

The architecture and/or functionality of the various previous figuresmay be implemented in the context of a general computer system, acircuit board system, a game console system dedicated for entertainmentpurposes, an application-specific system, and/or any other desiredsystem. For example, the system 465 may take the form of a desktopcomputer, a laptop computer, a tablet computer, servers, supercomputers,a smart-phone (e.g., a wireless, hand-held device), personal digitalassistant (PDA), a digital camera, a vehicle, a head mounted display, ahand-held electronic device, a mobile phone device, a television,workstation, game consoles, embedded system, and/or any other type oflogic.

While various embodiments have been described above, it should beunderstood that they have been presented by way of example only, and notlimitation. Thus, the breadth and scope of a preferred embodiment shouldnot be limited by any of the above-described exemplary embodiments, butshould be defined only in accordance with the following claims and theirequivalents.

Machine Learning

Deep neural networks (DNNs) developed on processors, such as the PPU 200have been used for diverse use cases, from self-driving cars to fasterdrug development, from automatic image captioning in online imagedatabases to smart real-time language translation in video chatapplications. Deep learning is a technique that models the neurallearning process of the human brain, continually learning, continuallygetting smarter, and delivering more accurate results more quickly overtime. A child is initially taught by an adult to correctly identify andclassify various shapes, eventually being able to identify shapeswithout any coaching. Similarly, a deep learning or neural learningsystem needs to be trained in object recognition and classification forit get smarter and more efficient at identifying basic objects, occludedobjects, etc., while also assigning context to objects.

At the simplest level, neurons in the human brain look at various inputsthat are received, importance levels are assigned to each of theseinputs, and output is passed on to other neurons to act upon. Anartificial neuron or perceptron is the most basic model of a neuralnetwork. In one example, a perceptron may receive one or more inputsthat represent various features of an object that the perceptron isbeing trained to recognize and classify, and each of these features isassigned a certain weight based on the importance of that feature indefining the shape of an object.

A deep neural network (DNN) model includes multiple layers of manyconnected perceptrons (e.g., nodes) that can be trained with enormousamounts of input data to quickly solve complex problems with highaccuracy. In one example, a first layer of the DLL model breaks down aninput image of an automobile into various sections and looks for basicpatterns such as lines and angles. The second layer assembles the linesto look for higher level patterns such as wheels, windshields, andmirrors. The next layer identifies the type of vehicle, and the finalfew layers generate a label for the input image, identifying the modelof a specific automobile brand.

Once the DNN is trained, the DNN can be deployed and used to identifyand classify objects or patterns in a process known as inference.Examples of inference (the process through which a DNN extracts usefulinformation from a given input) include identifying handwritten numberson checks deposited into ATM machines, identifying images of friends inphotos, delivering movie recommendations to over fifty million users,identifying and classifying different types of automobiles, pedestrians,and road hazards in driverless cars, or translating human speech inreal-time.

During training, data flows through the DNN in a forward propagationphase until a prediction is produced that indicates a labelcorresponding to the input. If the neural network does not correctlylabel the input, then errors between the correct label and the predictedlabel are analyzed, and the weights are adjusted for each feature duringa backward propagation phase until the DNN correctly labels the inputand other inputs in a training dataset. Training complex neural networksrequires massive amounts of parallel computing performance, includingfloating-point multiplications and additions that are supported by thePPU 200. Inferencing is less compute-intensive than training, being alatency-sensitive process where a trained neural network is applied tonew inputs it has not seen before to classify images, translate speech,and generally infer new information.

Neural networks rely heavily on matrix math operations, and complexmulti-layered networks require tremendous amounts of floating-pointperformance and bandwidth for both efficiency and speed. With thousandsof processing cores, optimized for matrix math operations, anddelivering tens to hundreds of TFLOPS of performance, the PPU 200 is acomputing platform capable of delivering performance required for deepneural network-based artificial intelligence and machine learningapplications.

Exemplary Runtime Testing Environment

FIG. 5 illustrates an exemplary computing environment 500 during aruntime (e.g., online) test, according to one exemplary embodiment. Asshown, an integrated circuit 502 includes a plurality of computingclusters 504A-N, where each of the plurality of computing clusters504A-N includes a plurality of independent processing elements 506A-N,508A-N, and 510A-N.

Additionally, a system software scheduler 512 is in communication withthe integrated circuit 502. In one embodiment, the system softwarescheduler 512 distributes application-specific computing tasks to eachof the independent processing elements 506A-N, 508A-N, and 510A-N withinthe integrated circuit 502.

Further, in one embodiment, during or after an initial boot of theintegrated circuit 502, test vectors are transferred from a first (e.g.,volatile or non-volatile) storage 516 to a second (e.g., volatile ornon-volatile) storage 518 within the integrated circuit 502. In anotherembodiment, in response to a predetermined schedule or safety standard,the system software scheduler 512 may distribute testing tasks(different from application-specific computing tasks) to selectedindependent processing elements 506A, 508B, and 510N within each of theplurality of computing clusters 504A-N. The remaining independentprocessing elements within the plurality of computing clusters 504A-Nmay continue to receive and execute application-specific computingtasks.

In response to receiving the testing tasks from the system softwarescheduler 512, the selected independent processing elements 506A, 508B,and 510N may be taken offline. Additionally, in response to the selectedindependent processing elements 506A, 508B, and 510N being takenoffline, the test vectors preloaded into the volatile storage 518 withinthe integrated circuit 502 may be transferred to each of the selectedindependent processing elements 506A, 508B, and 510N, and may be used totest the functionality of the selected independent processing elements506A, 508B, and 510N in parallel. In one embodiment, before transferringthe test vectors, one or more security mechanisms may determine whetherthe test vectors have been tampered with (e.g., altered, etc.). Thesecurity mechanisms may also prevent transfer of the test vectors inresponse to determining that the vectors have been tampered with.

Further still, in one embodiment, while the testing of the selectedindependent processing elements 506A, 508B, and 510N is being performedin parallel, the remaining independent processing elements within theintegrated circuit 502 may continue to receive and executeapplication-specific computing tasks.

Also, in one embodiment, in response to determining, via the testing,that the selected independent processing elements 506A, 508B, and 510Nare functional, such processing elements may be brought back onlinewithin the integrated circuit 502. Once such processing elements areback online, they may proceed to receive and executeapplication-specific computing tasks from the system software scheduler512.

In this way, the selected independent processing elements 506A, 508B,and 510N may be tested during run time while the remaining independentprocessing elements within the integrated circuit 502 continue theirfunctional operation. This may improve a performance of the integratedcircuit 502 since the integrated circuit 502 may avoid being takencompletely offline to perform such testing.

FIG. 6 illustrates an exemplary scan architecture 600 for a singlepartition, according to one embodiment. As shown, the scan architecture600 includes a plurality of scan chains 602 that are fed from apseudo-random pattern generator (PRPG) 604 and that produce responsescaptured by a multiple input shift register (MISR) 606.

In one embodiment, when the exemplary scan architecture 600 is in a testmode, a clock used for all scan chains 602 switches to a serdes slowclock 608 that is fed into a multiplexer 610. This provides a singleclock source that feeds all scan chains 602. However, since all scanchains 602 are synchronized to the serdes slow clock 608, all scanchains 602 toggle in unison, which may create an undesirable voltagedrop.

One exemplary solution includes utilizing a serdes fast clock 612 todrive the scan chains 602, and manipulating clock gaters located betweenthe multiplexer 610 and the scan chains 602 to shift resulting waveformsof different portions of the scan chains 602. This may result in thecreation of different clipped clocks for predetermined portions of thescan chains 602, which may reduce an amount of voltage drop created bythe scan chains 602 during scanning.

FIG. 7 illustrates an exemplary CPU cluster 700, according to oneembodiment. As shown, the CPU cluster 700 includes a plurality of cores702A-D, each with a plurality of partitions 704A-D, 706A-D, 708A-D, and710A-D. In order to minimize the voltage drop from each partition, clockgaters within each partition may be manipulated to adjust their timingcreated by the associated scan clocks.

For example, a first core 702A has four partitions 704A-D. To minimize avoltage drop for a first partition 704A, the first partition 704A isdivided into four regions 712A-D. Clock gaters within each of theseregions 712A-D are manipulated such that the timing of the associatedscan clocks within one region do not overlap with the remaining regionswithin the partition 704A. In this way, an amount of voltage dropcreated by the first partition 704A during scanning may be reduced.

FIG. 8 illustrates an exemplary staggering 800 of clocks acrossquadrants of a partition of a processing core, according to oneembodiment. As shown, within a single partition of a processing core, aserdes slow clock 802 is bypassed and a serdes fast clock 804 is fedinto clock gaters of the partition. Additionally, test enable ports ofall clock gaters are connected to a controller, and the controllersgenerate different signals 806A-D for each quadrant of the partition.

Further, combining the serdes fast clock 804 with each of the differentsignals 806A-D created by the controllers results in different clippedclocks 808A-D for each quadrant of the partition. This creates staggeredclocks within the partition that reduces an amount of voltage dropduring the scanning of the single partition of the processing core.

FIG. 9 illustrates an exemplary quadrant grouping within a partition900, according to one embodiment. As shown, a fast clock 902 drivesgaters 904A-D for each of a plurality of quadrants 906A-D of thepartition 900. This results in four different groups of scan clocks908A-D, where each group of scan clocks 908A-D produce a clipped clockwith a different timing from the other groups. This results in staggeredclocks within the partition 900.

Regional Low-Power-Shift-Stagger for In-System-Test Functional SafetyMechanisms

Peak power consumption and IR drop due to high toggle rates during scanshift operation are a significant concern to test quality andreliability. This is an even bigger issue for function safety mechanismslike Online-IST that rely on running DFT based structural scan tests onone CPU core while rest of the CPU cores are fully functional executingmission mode applications.

The high toggle-rate on CPU-under-test (physically implemented as one ormore partitions) causes a voltage drop resulting in timing failures onneighboring functional CPU cores sharing the same voltage rail. Thelocal IR drop becomes worse as the partition sizes grow. Online-IST as afunctional safety mechanism needs to operates seamlessly like anyanother functional application without degrading mission mode power andperformance metrics. The toggle-rate localized to CPU core-under-testmust be close to functional toggle-rates (8 to 12%) which is much lowerthan the test mode toggle-rates (50%).

Scan Architecture Overview

Scan chains are stitched between PRPG and MISR and test data feeds intothe PRPG from N:4N deserializer. The input interface of the deserializeroperates on serdes_fast_clk (˜250 MHz) whereas the PRPG and MISR operateon serdes_slow_clk (62.5 MHz, serdes_fast_clk/4). The serdes_slow_clk ismuxed on to the functional clock tree inside the clock macro and clocksall the flops on scan chains.

Partition Regioning

Each partition is divided into multiple regions (e.g., N), and flops ina region are stitched together with a MISR per region and the shiftclock is staggered across the groups. Only flops in a partition grouptoggle on a clock edge reducing activity by factor of N while achievingspatial separation. For Orin, N is 4 and partition is divided intoquadrants to get to a desired toggle rate.

Staggering Region Clocks

Functional clock-gaters (CGs) driving flops in each region are groupedand their enables are controlled uniquely to derive staggered clocksacross the regions. Serdes_fast_clk is sourced as shift clock and theCGs downstream of the clock macro receive the free runningserdes_fast_clock. The TE pins of CGs belonging to a quad are drivenfrom the respective quad's XTR IP. Across the quads, TE pins arecontrolled such that the clocks are staggered. Though a faster clock isused, the flops are still clocked at serdes_slow_clk frequency.

Clock Gate Handling

A TE pin which used to be scan_en is now a dynamic signal. An enable pincan control the CG while TE is low which breaks shift operation. Toavoid this, CGs are replaced with TD-type CGs.

Placement Considerations

CGs may be placed to satisfy timing requirements on both the E and TEpins. The path from XTR IP to CG TE pin may meet serdes_fast_clk timing.When hierarchical CGs are present on a clock path, the CGs closer to theroot of distribution are replaced with TD-type CGs to minimize thetiming impact. Scan chains cannot be re-ordered across the quadrants.

Addressing Timing Challenges

The duty cycle of the clock makes the setup timing tight on chains withpos-edge flops followed by neg-edge flops, however there are no neg-edgescan flops in CPU core. A compensation flop on a Quadrant-0 clock isadded at the beginning of the Quadrant-2 to ease the hold timing betweenPRPG and scan flop.

Working Around EDA Tool Limitations

The proposed stagger scheme is not understood by the EDA tool and thepatterns must be generated on slow_clock without any region stagger. Itis imperative that when the staggering is enabled, flops get loaded withthe same values as in the tool generate pattern. A compensation flop onQuad-0 clock is added at the beginning of the Quad-3 chains as PRPGdrives data on neg-edge of the serdes_slow_clock and flops in Quad-3 getupdated with the next pattern data resulting in failures. The quad-2 and3 MISRs clock is delayed by one cycle to ensure that the correctsignature is computed. Every scan flop should have a CG on its clockpath otherwise it will be clocked four times in one shift cycle whichmay result in failures. In the CPU core, the majority of the flops arefunctionally clock gated. DFT-CGs are inserted for the un-gated flops.

In one embodiment, local IR drop can be further improved if the groupsare spatially spread out across the partition rather than beingquadrants.

In this way, IR drop may be reduced at a local level (within apartition) instead of a coarser level (across partitions). This mayreduce typical scan shift toggle rates to align to functional togglerates by reusing existing clock sources and functional clock gateswithout requiring any new clock sources for functional IP. This seamlessintegration into existing ASIC flows with no adverse mission modeperformance or power penalty. Also, the scheme is ATPG EDA tool agnosticand does not require any tool enhancements.

While various embodiments have been described above, it should beunderstood that they have been presented by way of example only, and notlimitation. Thus, the breadth and scope of a preferred embodiment shouldnot be limited by any of the above-described exemplary embodiments, butshould be defined only in accordance with the following claims and theirequivalents.

The disclosure may be described in the general context of computer codeor machine-useable instructions, including computer-executableinstructions such as program modules, being executed by a computer orother machine, such as a personal data assistant or other handhelddevice. Generally, program modules including routines, programs,objects, components, data structures, etc., refer to code that performparticular tasks or implement particular abstract data types. Thedisclosure may be practiced in a variety of system configurations,including hand-held devices, consumer electronics, general-purposecomputers, more specialty computing devices, etc. The disclosure mayalso be practiced in distributed computing environments where tasks areperformed by remote-processing devices that are linked through acommunications network.

As used herein, a recitation of “and/or” with respect to two or moreelements should be interpreted to mean only one element, or acombination of elements. For example, “element A, element B, and/orelement C” may include only element A, only element B, only element C,element A and element B, element A and element C, element B and elementC, or elements A, B, and C. In addition, “at least one of element A orelement B” may include at least one of element A, at least one ofelement B, or at least one of element A and at least one of element B.Further, “at least one of element A and element B” may include at leastone of element A, at least one of element B, or at least one of elementA and at least one of element B.

The subject matter of the present disclosure is described withspecificity herein to meet statutory requirements. However, thedescription itself is not intended to limit the scope of thisdisclosure. Rather, the inventors have contemplated that the claimedsubject matter might also be embodied in other ways, to includedifferent steps or combinations of steps similar to the ones describedin this document, in conjunction with other present or futuretechnologies. Moreover, although the terms “step” and/or “block” may beused herein to connote different elements of methods employed, the termsshould not be interpreted as implying any particular order among orbetween various steps herein disclosed unless and except when the orderof individual steps is explicitly described.

1. A method comprising, at a device: staggering clocks within aplurality of portions of a computing element to form a plurality ofdifferent waveforms each corresponding with a different portion of theplurality of portion of the computing element; and performing testing ofthe computing element, utilizing the staggered clocks.
 2. The method ofclaim 1, wherein the computing element includes a single partition of asingle processing core.
 3. The method of claim 2, wherein the singleprocessing core is one of a plurality of processing cores within asystem.
 4. The method of claim 2, wherein the single processing coreincludes a single independent processing core selected from a cluster ofindependent processing cores that are currently performingapplication-specific operations.
 5. The method of claim 1, whereinstaggering the clocks within the computing element includes creating aplurality of different clipped clocks within the computing element. 6.The method of claim 5, wherein a clipped clock is created for eachportion of the plurality of portions of the computing element, and whereeach of the clipped clocks has a different waveform of the plurality ofdifferent waveforms.
 7. The method of claim 1, wherein staggering theclocks is performed utilizing an existing clock source within a system.8. The method of claim 5, wherein a clipped clock is created for aportion of the computing element by manipulating one or more clockgaters within the portion to generate a corresponding waveform of theplurality of different waveforms.
 9. The method of claim 8, wherein themanipulated clock gaters within the portion are driven by a fast clockwithin a system to create the clipped clock within the portion.
 10. Themethod of claim 6, wherein each of the plurality of portions of thecomputing element are tested utilizing the clipped clock correspondingto the portion.
 11. The method of claim 6, wherein an input signal isprovided to each of the plurality of portions of the computing element,utilizing the clipped clock corresponding to each portion.
 12. Themethod of claim 11, wherein each of the plurality of portions of thecomputing element produce output based on the provided input signal. 13.A system comprising: a hardware processor of a device that is configuredto: stagger clocks within a plurality of portions of a computing elementto form a plurality of different waveforms each corresponding with adifferent portion of the plurality of portion of the computing element;and perform testing of the computing element, utilizing the staggeredclocks.
 14. The system of claim 13, wherein the computing elementincludes a single partition of a single processing core.
 15. The systemof claim 14, wherein the single processing core is one of a plurality ofprocessing cores within a system.
 16. The system of claim 14, whereinthe single processing core includes a single independent processing coreselected from a cluster of independent processing cores that arecurrently performing application-specific operations.
 17. The system ofclaim 13, wherein staggering the clocks within the computing elementincludes creating a plurality of different clipped clocks within thecomputing element.
 18. The system of claim 17, wherein a clipped clockis created for each portion of the plurality of portions of thecomputing element, and where each of the clipped clocks has a differentwaveform of the plurality of different waveforms.
 19. A non-transitorycomputer-readable storage medium storing instructions that, whenexecuted by a processor of a device, causes the processor to cause thedevice to: stagger clocks within a plurality of portions of a computingelement to form a plurality of different waveforms each correspondingwith a different portion of the plurality of portion of the computingelement; and perform testing of the computing element, utilizing thestaggered clocks.
 20. The non-transitory computer-readable storagemedium of claim 19, wherein the computing element includes a singlepartition of a single processing core.
 21. The method of claim 1,wherein each of the clocks includes a clock generator that generatespulses used to synchronize operations within the computing element. 22.The method of claim 1, wherein staggering the clocks results in theshifting of waveforms across the plurality of portions of the computingelement.
 23. The method of claim 1, wherein the clocks are staggered tocreate different timings across the plurality of portions of thecomputing element.
 24. The method of claim 23, wherein clock gaterswithin the plurality of portions of the computing element aremanipulated to stagger the clocks such that the timings of scan clockswithin the plurality of portions of the computing element do not overlapwith one another.